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jmfine

About

Username: jmfine
Joined: April 2017
Visits: 1
Last Active: April 2017
Roles: Member

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I created a simple code to try and figure out the problem Prepare phase: from ctypes import windll global io io=windll.dlportio port=0xB010 Run phase: io.DlPortWritePortUchar(port, 255) clock.sleep(0.01) io.DlPortWritePortUchar(port, 0) clock.sl…

in Trigger problem, but only when running experiment Comment by jmfine April 2017